1. Field of the Invention
The present invention relates to a semiconductor LSI (Large-Scale Integration) circuit and a method for fabricating the semiconductor LSI circuit. More specifically, it relates to a semiconductor LSI circuit having basic logic gates with a highly integrated and microscopic structure, such as a NAND gate and a NOR gate.
2. Description of the Related Art
A conventional basic device having an LSI logic region made up of basic logic gate circuits such as a NAND gate and a NOR gate has a basic structure using a complementary metal-oxide semiconductor (CMOS), as shown in FIG. 1. As shown in FIG. 1, a conventional CMOS structure is fabricated by forming a well region 74 on a semiconductor substrate 72, a device isolating region 54, such as shallow trench isolation (STI). Then, an nMOSFET having n+ diffusion regions 64 and 66 as source and drain regions, respectively, and a pMOSFET having p+ diffusion regions 70 and 68 as source and drain regions, respectively connected to a common input terminal 50 and gate electrodes 56 and 60 formed on the semiconductor substrate 72 via respective gate insulating layers 58 and 62. The drain regions 66 and 68 are connected to a common output terminal 52. The CMOS structure shown in FIG. 1 can form a CMOS inverter by connecting the n+ diffusion region 64 of the nMOSFET to ground potential VSS (not shown in the drawing) and the p+ diffusion region 70 of the pMOSFET to power supply voltage VDD (not shown in the drawing). On the other hand, fabrication of a NAND gate or a NOR gate requires two CMOS structures or four MOSFETs.
A compact CMOS structure may be provided by forming a common metallic region as drain regions of a pMOSFET and an nMOSFET (e.g., Japanese Patent Application Laid-Open No. 2002-289697). This structure provides only a NOT gate.
A structure of a semiconductor device including a threshold-controllable thin-film transistor (TFT) with multiple layers of a back gate electrode, a first gate insulating layer, an active semiconductor layer, a second gate insulating layer, and a gate electrode formed on an insulating substrate has been disclosed (e.g., Japanese Patent Application Laid-Open No. 2001-51292). The above disclosure shows the back gate electrode only used for correcting a threshold voltage, but does not disclose a basic logic gate, which utilizes a double-gate structure.